Much like how humans moved from living in individual huts to multi-storied buildings, the silicon world is also transforming from hosting features in flat structures to 3-D structures. Moore’s Law, the guiding principle of how the industry has evolved, is facing headwinds as we approach the sub-3nm era and the necessity to uphold the law is making engineers innovate. This need is being driven by the insatiable demand from consumers like us who want to get more processing power in our hands without paying for the energy needed to compute at faster rates. As a result, semiconductor engineers have started stacking silicon die in the form of towers to pack features in the smallest area possible.


In the sub-3nm era, the semiconductor industry is experiencing a significant transformation that is pushing the boundaries of the complex interplay between physics, materials science, and engineering, particularly as we enter domains where classical physics intersects with quantum mechanics.

The adoption of sub-3nm nodes is not merely about miniaturization but calls for a paradigm shift in transistor architecture. For instance, Intel's 3 process represents possibly the last node using FinFET before transitioning to Intel's RibbonFET1 architecture, an indicator of the evolving fabrication technologies​​. Samsung has also been proactive in this space, having started initial production of high-performance chips using 3 nm process technology with Gate-All-Around (GAA) architecture as of June 2022​.


This feat by Samsung was made possible by the Gate-All-Around (GAA) transistors, including nanowire FETs and nanosheet FETs. Nanowire FETs utilize tiny wires for channels, whereas nanosheet FETs employ sheet-like materials. These structures provide improved gate control, enhancing performance and minimizing leakage, a vital attribute for continued scaling​​. Nanosheets offer significant advantages over finFETs in terms of channel control, despite apparent minimal scaling benefits between 3nm finFETs and nanosheets​​.


The development of these advanced transistors is a key indicator of the industry's commitment to innovation, as it moves towards even more intricate architectures like CFETs and vertical nanowires. In this context, we will explore the promise a tall-thin silicon architecture holds for the future.

Vertical Stacking: A Tall Claim?


Vertical stacking in semiconductors is like building skyscrapers instead of single-story houses. This method stacks transistors and other parts on top of each other (the Z-axis), making chips more compact and efficient. It helps pack more components into a small space and makes connections between them shorter and faster. 


This spatial optimization translates to shorter and more efficient pathways for electronic signals, drastically reducing the latency and power consumption typically associated with longer interconnects. This is key for tiny, sub-3nm chips, as it boosts computing power, saves energy, and adds more functions to small chips, crucial for things like advanced computing and wearables​​​​.3 The result is a notable augmentation in the chip's computational prowess and energy efficiency—a critical factor in applications demanding high processing power within minimal form factors.


This is not a revolutionarily new idea though. As early as 2015, Stanford engineers unveiled the Skyscraper-style chip design that boosts performance by a factor of a thousand.4 Imagine a smartwatch that's 5x thinner yet offers 100x faster computing power, thanks to vertically stacked silicon chips. This technology enables devices like ultra-slim laptops to perform complex tasks like real-time 4K video editing or running advanced AI algorithms, tasks that once required a high-end desktop. This leap in efficiency and power in such compact devices revolutionizes how we interact with technology in our daily lives.


However, this vertical stacking approach has its own challenges. Packing components so closely can cause overheating, make power delivery complex, and complicate chip-making and testing. Plus, at these tiny scales, quantum effects come into play, requiring new materials and design methods to manage these issues effectively​​​​. We will explore the various problems of vertical stacking architectures and their potential solutions. 

Power Delivery Issues:

In vertically stacked silicon, ensuring power delivery to each System on Chip (SoC) layer stacked atop one another is a key challenge. Every chip, with its myriad of transistors, requires a stable power supply to operate optimally. As we venture into the era of ultra-thin, vertically integrated semiconductor structures, the task of uniformly and efficiently supplying power to each layer of the stack becomes increasingly complex. This complexity stems from the increased density of transistors and the intricate architecture of these multi-layered systems.


Through-Silicon Vias (TSVs), which are essentially micro-scale vertical interconnects, play a crucial role in addressing the power delivery limitations in vertically stacked silicon structures. TSVs function as conduits for both signal and power transmission across the various layers of an SoC, effectively forming the backbone of the chip's internal power distribution network. Their significance in 3D IC production has been exemplified by their use in CMOS image sensors, DRAM, and other semiconductor applications by leading companies such as Toshiba, Samsung, and SK Hynix​​.


However, the use of TSVs in the context of sub-3nm chips introduces new challenges. One significant issue is electromigration, a phenomenon exacerbated in smaller TSVs due to their higher current density relative to their size. The problem of electromigration is particularly acute in regions where TSVs taper5, leading to increased current density and subsequent void formation, potentially resulting in circuit failure​.

Signal Integrity and Crosstalk Concerns


Another concern with vertically stacked silicon architecture is maintaining signal integrity and managing crosstalk. As transistors and other components are positioned closer together in the vertical axis, the potential for electromagnetic interference between high-speed signals escalates. This interference, known as crosstalk, can significantly impact the performance of the chip by causing signal degradation.


Addressing these concerns requires a sophisticated understanding of electromagnetic coupling and the implementation of advanced design strategies. Crosstalk in vertically stacked silicon occurs primarily due to capacitive and inductive coupling between signal lines. Capacitive coupling is when the signal from one line interferes with another through a capacitor-like effect, while inductive coupling occurs through an inductor-like interaction between lines. Both phenomena can lead to signal distortion and loss of integrity, posing significant challenges in high-density chip designs.


Several strategies have been developed to mitigate crosstalk and preserve signal integrity. One such approach involves the use of dummy metal fill, which helps to isolate signal lines from each other, reducing the likelihood of interference. Moreover, 3D full-wave modeling and simulation of Through-Silicon Vias (TSVs) have been used to characterize and predict crosstalk under various configurations and conditions. This modeling enables the optimization of TSV design and placement, reducing the impact of crosstalk in high-frequency applications.


In addition to physical design alterations, electrical characterization techniques, such as evaluating S-parameters (reflection and transmission coefficients), are utilized to assess and optimize the signal integrity of the interconnections. With the help of simulated data streams through the TSVs and analyzing eye diagrams, engineers understand the impact of design choices on signal integrity and make informed adjustments.


To ensure the maximum system performance, it's crucial to consider the role and location of signal and ground Vias in the 3D design. Adjusting these parameters can significantly reduce the magnitude of crosstalk, particularly in high-frequency applications where crosstalk can be most detrimental. Other Solutions To Reduce Crosstalk:


  • Advanced Shielding Techniques: Employing shielding methods at the chip level to isolate signal paths physically and reduce the impact of electromagnetic interference.
  • Improved Circuit Design: Optimizing circuit layouts to minimize the proximity of high-speed signal lines and employing differential signaling where possible to reduce susceptibility to crosstalk.
  • Material Innovations: Exploring advanced materials with better electromagnetic properties for use in chip fabrication, which could inherently reduce crosstalk and improve signal integrity.
  • Signal Conditioning: Using signal conditioning techniques such as buffering and the use of repeaters to strengthen signal integrity over longer distances within the chip.
  • Alternative Interconnect Technologies: Exploring other interconnect technologies beyond TSVs, such as optical interconnects or wireless chip-to-chip communication, which might offer different trade-offs in terms of signal integrity and crosstalk.
  • Dynamic Signal Management: Implementing intelligent systems within the chip that can dynamically adjust signal strength and routing based on real-time analysis of signal integrity and crosstalk levels.

Testability Trials:

The assembly of silicon layers in a vertically stacked configuration significantly complicates traditional testing methodologies. In conventional semiconductor designs, each input/output (I/O) is directly accessible, allowing for relatively straightforward testing processes. In vertically stacked chips, direct physical access to individual layers and their components is inherently limited. This constraint demands innovative approaches to test each layer thoroughly. To address the accessibility challenge, special test circuits are often integrated within the stacked layers. These circuits are designed to facilitate testing procedures by providing access points or test interfaces that can probe and evaluate the functionality of each layer. Vertically stacked designs also necessitate rigorous thermal and stress testing, as these structures can experience significant thermal and mechanical stress, affecting their performance and reliability. Other solutions and options that overcome the limitations of a vertically stacked architecture are:


  • Contactless Testing: Investigating the potential of contactless testing methodologies, such as capacitive or inductive coupling, to perform tests without physical contact with each layer.
  • Use of Simulation and Modeling: Given the physical constraints, simulation6, and modeling play a significant role in testing vertically stacked silicon. These tools can predict how the chip will behave under various conditions, helping to identify potential issues before physical testing.
  • New Testing Techniques: Techniques such as Built-In Self-Test (BIST) and Design for Testability (DFT) become crucial7. BIST involves integrating test circuits that can perform self-checks, while DFT strategies involve designing the chip in a way that makes it easier to test, such as adding test points or scan chains.
  • Advanced Probe Cards: Another solution is the development of sophisticated probe cards capable of interfacing with vertically stacked structures. These probe cards must be highly precise to align with the densely packed I/Os of each layer.
  • Electrical and Optical Testing Methods: Combining electrical testing with optical methods such as Infrared (IR) thermal imaging to identify faults and hotspots within the vertical stack is another possible solution here.
  • Fault Isolation Techniques: Advanced fault isolation techniques are required to pinpoint defects within a stack. Techniques such as Focused Ion Beam (FIB) and Scanning Electron Microscopy (SEM) can be used for this purpose.
  • 3D Testing Technologies: The industry leaders are also exploring advanced 3D testing technologies that can probe multiple layers simultaneously. These technologies may include electromagnetic probing, which can test the functionality of circuits without requiring physical contact.

Quality Quandary:

The quality of the final product in a vertically stacked silicon architecture is highly dependent on the integrity of each component in the stack. This interdependence significantly amplifies the importance of maintaining high quality across all layers of the silicon stack. Key aspects and challenges include:


  • Layer-to-Layer Variability: Variations in the manufacturing process across different layers can lead to inconsistencies in material properties, impacting the overall performance and reliability of the chip.
  • Thermal Management: As these stacked chips have a higher density, they generate more heat. Efficient thermal management is crucial, as overheating can lead to performance degradation and reliability issues.
  • Interlayer Connectivity: The quality of connections between layers, such as through-silicon vias (TSVs), is critical. Defects in these connections can lead to electrical failures or signal integrity issues.
  • Stress and Strain: The mechanical stress and strain induced during the fabrication and operation of these chips can impact their structural integrity and functioning. For example, stress-induced deformation can affect the alignment of layers, leading to functional defects.
  • Design Complexity: The design of vertically stacked chips is inherently more complex, which can introduce more points of potential failure. Advanced design techniques and fault-tolerant architectures are employed to mitigate these risks.

Yield and Cost Implications

The direct implication of the quality concern discussed above is reflected in the net yield and the business viability of this architecture. In vertically stacked silicon, such as 3D Integrated Circuits (ICs), yield losses can occur at two main stages: during the fabrication of individual stacked dies and during the assembly process. The precision required in aligning and bonding these multiple layers of silicon is intricate, with a very low margin for error. Misalignments or bonding defects can lead to functional failures of the entire stack.


The cost implications are directly linked to these yield challenges. Higher precision in manufacturing and assembly naturally increases production costs. Additionally, each defective layer in a stack can potentially render the entire chip unusable, leading to higher waste and thus increased costs. To mitigate these issues, the semiconductor industry employs various strategies:


  • Fault Tolerance Techniques: Incorporating fault tolerance in the design of vertically stacked ICs can help in managing yield losses. This involves designing chips in a way that they can still function correctly even if some parts are defective.
  • Hierarchical Testing and Inspection: Implementing rigorous testing at each stage of the fabrication and assembly process helps in the early detection of defects, thereby reducing the number of defective final products.
  • Design Optimization: Modifying the design of ICs, such as through cost-effective Through-Silicon Via (TSV) grouping, can improve yield by reducing the complexity and potential points of failure in the stack.


The advancements in these areas aim to balance the trade-off between the increased performance capabilities of vertically stacked architectures and their manufacturing and assembly complexities.

A Trusted Partner Needed To Stay Ahead and On Top

The transition to vertical stacked architecture in semiconductor technology represents not just a technological leap, but a fundamental shift in chip manufacturing and application. This shift is crucial as the industry ventures beyond the 2nm threshold, moving into the vertical dimension is almost a reinvention of the silicon engineering process. 


Quest Global, with its extensive expertise in semiconductor technology, is strategically positioned to help navigate its clients through these multi-layered challenges. Leveraging a deep understanding of the intricacies of silicon engineering, Quest Global's teams are equipped to partner with industry leaders in addressing the complexities inherent in the transition to sub-3nm chip technologies. Our commitment to extending the legacy of Moore's Law through this evolutionary leap positions us as a reliable and trustworthy partner for silicon engineering. If you have any further points or questions on this topic, I would love to hear from you. Reach out to me at [email protected]



  1. https://www.eenewseurope.com/en/intel-renames-manufacturing-nodes-tips-ribbonfet-powervia/
  2. https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture
  3. https://www.nature.com/articles/s41928-021-00583-z
  4. https://biox.stanford.edu/highlight/skyscraper-style-chip-design-boosts-performance-factor-thousand
  5. https://resources.system-analysis.cadence.com/blog/what-influences-through-silicon-via-tsv-reliability
  6. https://dl.acm.org/doi/fullHtml/10.1145/3568957
  7. https://siliconvlsi.com/built-in-self-test-bist/

Tall Thin Silicon In The Sub-3nm Era


Taher Madraswala

Strategic Client Partner, Quest Global

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