An effective design and verification methodology for digital PLL
This Paper depicts an effective simulation methodology to overcome the spice simulation time overhead of digital dominant, low frequency Digital PLL (DPLL). A low power wide range Digital Phase-Locked Loop (DPLL) design for generating precise pixel clock from a noisy and low frequency horizontal synchronization signal (HSYNC) is described here. The basic design challenges faced by pixel clock generator are Noisy low-frequency reference clock and Very high Feedback frequency multiplication ratio. Here, the verification methodology of the DPLL is divided into different stages.
Digital blocks are designed and verified with stringent test cases using System Verilog and analog block models. Analog blocks are designed using normal spice simulation. 2. Co-simulation environment is used for sign-off.